| 摘要 |
A multi-issue processor comprises a plurality of issue slots (UC0, UC1, UC2 and UC3), each one of the plurality of issue slots having a plurality of functional units (FU0, FU1 and FU2) and a plurality of holdable registers (1 - 33 and 101 - 117). The plurality of issue slots comprises a first set of issue slots (UC1, UC2 and UC3) and a second set of issue slots (UC0), and the register file (RF0 and RF1) is accessible by the plurality of issue slots (UC0, UC1, UC2 and UC3). A location of at least a part of the plurality of holdable registers (1 - 33) in the first set of issue slots (UC1, UC2 and UC3) is different from a location of at least a corresponding part of the plurality of holdable registers (101 - 117) in the second set of issue slots (UC0). The holdable registers can prevent that the inputs of unused functional units change, which would result in unnecessary power dissipation. However, this increases the amount of state that has to be saved during interrupt handling. By varying the position of the holdable registers for different issue slots, less state saving may be required during interrupt handling, while maintaining a significant reduction in power consumption and improved performance. |
