发明名称 |
Semiconductor memory device equipped with control circuit for controlling memory cell array in non-normal operation mode |
摘要 |
A semiconductor memory device is provided with a memory cell array including memory cells being arranged in a shape of matrix and requiring a refresh operation. In the semiconductor memory device, a control circuit controls a timing of the refresh operation in accordance with an internal signal independently of an external signal and controlling the memory cell array in a non-normal operation mode different from a normal operation mode for writing data into the memory cell array and reading out data from the memory cell array. The control circuit starts the non-normal operation mode in response to a sequence of entry into the non-normal operation mode based on a predetermined first command signal, sets the non-normal operation mode in response to a sequence of setting the non-normal operation mode based on a predetermined second command signal, and thereafter, executes operation of the corresponding non-normal operation mode which is set.
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申请公布号 |
US2003198116(A1) |
申请公布日期 |
2003.10.23 |
申请号 |
US20020267670 |
申请日期 |
2002.10.10 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
SATO HIROTOSHI;TSUKUDE MASAKI |
分类号 |
G01R31/28;G01R31/3185;G11C7/22;G11C11/401;G11C11/406;G11C29/14;(IPC1-7):G11C7/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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