发明名称 EXCLUSIVEELOGICAL SUM CIRCUIT
摘要 PURPOSE:To increase a degree of integration with arithmetic quickened by composing a circuit of four complementary transistors and one resistance. CONSTITUTION:The 1st input terminal 25 is connected to bases of the 1st NPN transistor Tr27 and 1st PNP Tr29, the 2nd input terminal 26 is also connected to bases of the 2nd NPN Tr28 and 2nd PNP Tr30, and collectors of Trs 29 and 30 connected in common are connected to output terminal 33 and also connected to GND via resistance 32. Next, when terminals 25 and 26 are both ''0'', Trs 27 and 28 turns OFF and Trs 29 and 30 ON; no current is therefore supplied from power terminal 34 to resistance 32, so that terminal 33 will be ''0''. When terminal 25 is ''1'' and terminal 26''0'', on the other hand, Trs 27 and 39 turn ON to supply a current to resistance 32, so that terminal 33 will be ''1''. Further, terminal 25 is ''0'' and terminal 26 ''1'', output 33 is ''1'' and when terminals 25 and 26 are both ''1'', output 33 is ''0''.
申请公布号 JPS54105441(A) 申请公布日期 1979.08.18
申请号 JP19780012184 申请日期 1978.02.06
申请人 NIPPON TELEGRAPH & TELEPHONE 发明人 YAMANE MICHIHIRO;SHIYUDOU KEIZOU
分类号 H03K19/21 主分类号 H03K19/21
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