发明名称 |
FINITE FIELD ADDER OF IMPROVED LINEAR LOOP FEEDBACK SHIFT REGISTER STRUCTURE |
摘要 |
PURPOSE: A finite field adder of an improved linear loop feedback shift register structure is provided to increase a process speed without increasing the number of registers. CONSTITUTION: The first input cells(ACELL0-ACELL(m/2)-1) shift at least two first input data by responding to one clock signal while shifting the first input data. The second input cells(BCELL0-BCELL(m/2)-1) shift at least two second input data by responding to one clock signal while shifting the second input data. Output registers(Z0-Zm-1) store the result data according to an output value from the first and the second input cells. The clock signal, inputted to the first and the second input cells, is the same clock signal.
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申请公布号 |
KR20030082255(A) |
申请公布日期 |
2003.10.22 |
申请号 |
KR20020020906 |
申请日期 |
2002.04.17 |
申请人 |
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
KIM, WON JONG;KIM, SEUNG CHEOL;CHO, HAN JIN;LEE, GWANG YEOP |
分类号 |
G06F7/52;(IPC1-7):G06F7/52 |
主分类号 |
G06F7/52 |
代理机构 |
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地址 |
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