| 摘要 |
A digital PLL's stability and immunity to jitter are improved by deriving the correction to the state machine count from an average over several computations of the phase error. The PLL stability is improved by retaining all of the phase errors measured during a succession of plural phase measurement intervals. The plurality of phase errors thus obtained are averaged together, and the state machine internal count is corrected (updated) in accordance with this average, rather than according to an instantaneous phase error. As a result, the performance of the PLL is less susceptible to jitter-induced temporary excursions in the phase error, a significant advantage.
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