发明名称 |
Error correction circuit and method |
摘要 |
A circuit 202 for executing range shift-up/-down of pass metric values is provided as an additional circuit preceding to an ACS circuit 203 for adding and comparing branch metric computation values and preceding pass metric values and selecting the highest likelihood pass. It is thus possible to permit effective use of RAM bits by executing range shift-up and the accuracy of the effective bits of input data when it is necessary to expand the effective bits of the pass metric values, while executing range shift-down and increasing the accuracy of the input data when the effective bits of the pass metric values are not fully used.
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申请公布号 |
US6637004(B1) |
申请公布日期 |
2003.10.21 |
申请号 |
US20000487795 |
申请日期 |
2000.01.20 |
申请人 |
NEC CORPORATION |
发明人 |
MIZUNO TAKANORI;IMAEDA YOSHITERU |
分类号 |
H04L1/00;H03M13/23;H03M13/41;(IPC1-7):H03M13/03 |
主分类号 |
H04L1/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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