| 摘要 |
In a network where frequency synchronous lower bit rate signals are combined to form a high bit rate signal by using hierarchies of multiplexers, i.e., concatenated multiplexers of different bit rate levels, an apparatus is provided for adjusting the phase deviations that occur between data input signals and a common clock signal. In one embodiment, the apparatus includes delay lines for delaying the input signals of the multiplexers of the lower hierarchies.
|
