Method of testing for micro latch-up

摘要

A reliable method of testing a CMOS-based integrated circuit device having a low-impedance path between I/O pin(s) and GND for potential micro-latch-up. The test method detects a low impedance path between the integrated circuit device I/O pin(s) and GND(s) caused by a parasitic SCR that is not detectable using conventional latch-up detection test methods.