| 摘要 |
A method and apparatus for compensating a delay locked loop against signal timing variances after circuit initialization which cause delay shifts due to temperature and voltage changes and operational noise. A delay line of a delay locked loop is disclosed, the delay line having a plurality of delay elements and a minimum and maximum delay boundary. According to an embodiment of the invention, an artificial minimum or maximum boundary, or both, is established on the delay line such that during initialization of the delay locked loop circuit, the circuit cannot lock on a delay element beyond the artificial minimum or maximum boundaries. By offsetting the artificial minimum and maximum boundaries from the actual minimum and maximum boundaries of the delay line, a buffer of delay elements is established at the actual delay line boundaries. During operation of the delay locked loop apart from initialization, the artificial boundaries become transparent to the delay locked loop and are available for the circuitry to use if needed.
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