发明名称 |
Method for fabricating a MOS transistor using a self-aligned silicide technique |
摘要 |
A method for fabricating a MOS transistor using a self-aligned silicide technique is provided. The method includes forming a gate electrode and a silicidation resistant layer pattern that are sequentially stacked on a predetermined region of a semiconductor substrate. Impurities are implanted into the semiconductor substrate to form a source/drain region. A first metal silicide layer is selectively formed on the surface of the source/drain region. The silicidation resistant layer pattern is then removed to expose the gate electrode. A second metal silicide layer is selectively formed on the exposed gate electrode. Consequently, the first metal silicide layer can be formed of a metal silicide layer having superior tolerance with respect to junction spiking. Also, the second metal silicide layer can be formed of another metal silicide layer having a low variation of resistivity due to the variation of the line width of the gate electrode. Therefore, it is possible to fabricate a high-performance MOS transistor suitable for a highly integrated semiconductor device.
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申请公布号 |
US6635539(B2) |
申请公布日期 |
2003.10.21 |
申请号 |
US20020131418 |
申请日期 |
2002.04.22 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KWON HYUNG-SHIN;KIM DO-HYUNG |
分类号 |
H01L21/28;H01L21/336;H01L27/092;H01L29/423;H01L29/49;H01L29/78;(IPC1-7):H01L21/336;H01L21/320;H01L21/476 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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