| 摘要 |
A semiconductor device is disclosed, by which the parasitic capacitance of each signal line can be decreased, the time necessary for developing the device can be decreased, and which has a structure for simply and quickly performing the characteristic evaluation of the semiconductor device. The semiconductor device comprises a lower-layer signal line provided below one of a main power-supply line and a main ground line via an insulating layer; and an upper-layer signal line provided above said one of the main power-supply line and the main ground line via an insulating layer. A window is formed in said one of the main power-supply line and the main ground line; and the lower-layer signal line and the upper-layer signal line are electrically connected in a space inside the window, without contacting said one of the main power-supply line and the main ground line. |
