| 摘要 |
PROBLEM TO BE SOLVED: To easily perform layout correction for changing power source wiring in a circuit block. SOLUTION: This method for designing a semiconductor integrated circuit to the circuit block having a plurality of cells including circuit elements is provided with an RC calculation process for calculating parasitic resistance and parasitic capacitance of inter-cell wiring for connecting between cells, a delay calculation process for calculating delay to be generated on a path including the inter-cell wiring, a time margin calculation process for calculating an allowable range of delay time to be generated in the inter-cell wiring so that the circuit elements connected with the path including the inter-cell wiring are normally operated, a wiring length margin calculation process for calculating an allowable range of wiring length for each of the inter-cell wiring, a cell interval allowable range calculation process for calculating allowable ranges between cells by every interval of the cells and a power source wiring allocation process for varying allocation of power strap wiring in the circuit block by varying the cell intervals within the allowable ranges of the cell intervals. COPYRIGHT: (C)2004,JPO
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