发明名称 MATRIX ARITHMETIC PROCESSOR
摘要 PROBLEM TO BE SOLVED: To provide a matrix arithmetic processor capable of quickly executing a matrix arithmetic operation in a small circuit scale. SOLUTION: An input signal data column I is temporarily stored in a reg 12, and inputted to an adder in response to an instruction from a control means 10. The control means 10 instructs an ROM 11 in which a check matrix H is stored to obtain a position where '1' is erected in a certain column of the check matrix. The ROM 11 instructs selectors SEL1 #1 to #CW to select values corresponding to the position of 1 in the check matrix from among values from a reg(M) 13, and to transmit the values to the adder. The added values are selected by selectors SEL2 instructed by the ROM 11, and inputted to the reg(M) 13. As for non-added values, the output values of the reg(M) 13 are inputted as they are, or inputted through the selectors SEL2 to the reg(M). This process is repeated until all the arithmetic operations end. COPYRIGHT: (C)2004,JPO
申请公布号 JP2003296302(A) 申请公布日期 2003.10.17
申请号 JP20020098025 申请日期 2002.03.29
申请人 FUJITSU LTD 发明人 OTA MITSUHIKO
分类号 G06F17/16;H03M13/09;H03M13/19;(IPC1-7):G06F17/16 主分类号 G06F17/16
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