| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To easily and efficiently perform layout design while securing synchronizing operations among the respective functional blocks and among respective semiconductor integrated circuits in the semiconductor integrated circuits. <P>SOLUTION: Functional blocks BL are approximately arranged, wiring paths outside the blocks are approximately determined, the final delay time T is calculated as the sum of delay time Tout outside the blocks and delay time Tin inside the blocks, arrangement of the respective cells in the functional blocks, wiring paths CNin inside the blocks and the wiring paths CNout outside the blocks are determined so that clock skew for each cell is settled within a restricted range and the final delay time T is settled within a prescribed range and a wiring pattern is generated according to the determined wiring paths. In arranging the respective cells in the functional blocks BL and determining the wiring paths inside the blocks, a template expressing a clock tree CT is generated, the respective cells are allocated and the wiring paths are determined on the basis of the clock tree CT expressed on the template. <P>COPYRIGHT: (C)2004,JPO</p> |
