| 摘要 |
PURPOSE: A synchronous semiconductor memory device using an internal prefetch is provided which provides ordering as to multi bit prefetch data. CONSTITUTION: An assembly logic circuit part(101) receives input data and arranges them in sequence and then outputs them. A pipe register part(102) comprises M latches per bit, and stores and outputs the above arranged input data. An odd number shift register part(103) outputs odd-numbered data at a desired time among data being output from the pipe register part. An even number shift register part(104) outputs even-numbered data at a desired time among data being output from the pipe register part. And a multiplexing part(105) outputs the odd-numbered data and the even-numbered data by synchronizing to a clock edge.
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