| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a rake receiver the demodulation section of which has comparatively small circuit scale. <P>SOLUTION: Delay circuits 14a to 14c apply prescribed delay to an output from an ADC (analog digital converter) 10 and the delayed output is fed to a selection circuit 16. The selection circuit 16 sequentially selects signals from the three delay circuits 16 and supplies the selected signal to a DMOD (demodulator) 18. Then the DMOD 18 sequentially applies demodulation processing to the three signals in time division. In particulars the DMOD 18 performs the FWT (fast Walsh transform) arithmetic operation. After latch circuits 20a to 20c store demodulated data of each path obtained in time division, a composite circuit 22 composes the data, and selects a maximum value among the data subjected to demodulation processing in parallel by the DMOD 18. <P>COPYRIGHT: (C)2004,JPO</p> |
