| 摘要 |
<P>PROBLEM TO BE SOLVED: To solve the problem that precise control is impossible since a change in a frequency is wide in a clock generating circuit for selectively supplying a clock which is obtained by dividing the frequency of an output from a PLL (phase locked loop). <P>SOLUTION: A clock output S160 is generated by selecting, in a clock synthetic selector circuit 161, all the outputs of CMOS inverters 151-157 on odd- numbered stages constituting a voltage controlled oscillator 150 of a PLL 100, and a clock synthesizing control circuit 162 is provided for performing control to switch the selection in the clock synthetic selector circuit 161 for the even- numbered stages of CMOS inverters for each rising edge of the clock output S160. Thereby, the clock of a frequency with a little difference is generated before and after the state of fixing the oscillation frequency of the PLL 100. <P>COPYRIGHT: (C)2004,JPO |
