Conditional read and invalidate for use in coherent multiprocessor systems

摘要

A conditional read and invalidate operation for use in coherent multiprocessor systems is disclosed. A conditional read and invalidate request may be sent via an interconnection network from a first processor that requires exclusive access to a cache block to a second processor that requires exclusive access to the cache block. Data associated with the cache block may be sent from the second processor to the first processor in response to the conditional read and invalidate request and a determination that the cache block is associated with a state of a cache coherency protocol.