发明名称 Verification of a processor architecture having a partial instruction set.
摘要 <p>A method for verifying the architectural integrity of a newly written or modified instruction set in a limited operating environment is described. More particularly, this methodology is adapted to perform such verification even though the processor under test (14) has only one or a few instructions in its partially complete instruction set. Such verification is accomplished using a minimum test driver, under control of a test support processor (10), which loads the data necessary to execute the instruction being tested, into a memory (12) shared for access by both processors (10, 14). The test system also provides actual or simulated l/O capabilities. After execution of that instruction, the test driver directs capture of the execution results for appropriate use. As an aid in performing the verification test, the test driver is provided with an invalid command that forces return of control to the test processor (10). In operation, the processor (14) to be microcoded is tested instruction by instruction, via shared memory (12), with microcode corrections being made on the same basis to avoid error propagation into the remainder of the instruction set as it is developed.</p>
申请公布号 EP0111952(A2) 申请公布日期 1984.06.27
申请号 EP19830201660 申请日期 1983.11.23
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BUONOMO, JOSEPH PATRICK;PERRY, WENDELL LEE
分类号 G06F11/22;G06F11/26 主分类号 G06F11/22
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