MEMORY MANAGEMENT UNIT FOR DEVELOPING MULTIPLE PHYSICAL ADDRESSES IN PARALLEL FOR USE IN A CACHE

摘要

of The Disclosure A cache memory for use in a data processing system wherein data words are identified by either an odd or an even address number and wherein system elements request the transfer of data words with the cache memory by supplying either an odd or an even memory request address number with a memory request, the cache memory including a first plurality of addressable memory locations for storing data words associated with odd address numbers and a second plurality of memory locations for storing data words associated with even address numbers, and an adder for incrementing a memory request address number by one to generate the address number of the next successively stored data word to permit a set of memory address drivers to control the addressing and transferring of a data word stored in the first memory module and associated with an odd address number simultaneously with the addressing and transferring of a data word stored in the second memory module and addressed by an even address number.