发明名称 Semiconductor memory delay circuit
摘要 A circuit includes an input for receiving an input signal, a delay chain connected to the input for delaying the input signal, and a circuit configuration connected to the delay chain downstream of the input, the circuit configuration for supplying a voltage to the delay chain in response to the input signal.
申请公布号 US2003193359(A1) 申请公布日期 2003.10.16
申请号 US20030405357 申请日期 2003.04.03
申请人 CHO JI-HO;LEE SEUNG-KEUN 发明人 CHO JI-HO;LEE SEUNG-KEUN
分类号 H03K5/13;G11C8/18;H03K5/08;H03K5/1534;(IPC1-7):H03H11/26 主分类号 H03K5/13
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