发明名称 |
Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories |
摘要 |
An apparatus comprising a controller circuit and a BISR assembly circuit. The controller circuit may be configured to present one or more control signals. The control signals may be configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation. The BISR assembly circuit generally comprises one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution during the BIST and BISR operations. The memory blocks may be remapped in response to the count values during one or more of the BISR operations.
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申请公布号 |
US2003196143(A1) |
申请公布日期 |
2003.10.16 |
申请号 |
US20020120670 |
申请日期 |
2002.04.11 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
PURI MUKESH K.;AGRAWAL GHASI R. |
分类号 |
G06F11/00;G11C29/00;G11C29/16;G11C29/44;H04B1/74;(IPC1-7):H04B1/74 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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