Compensation scheme for reducing delay in a digital impedance matching circuit to improve return loss

摘要

A simple, power efficient and inexpensive digital compensation scheme for reducing delay in a digital impedance matching circuit to improve return loss. The scheme employs a digital filter to compensate for the absolute sampling and digital delays associated with a digital impedance matching circuit. The digital filter is based on the low-pass function of a DAC response, and can easily be modified to correct for not only the DAC response delay, but also other delays in the digital impedance matching circuit. The digital filter is very simple to implement and can add or subtract delays from the overall system.