发明名称 |
RAM with fewer address terminals than data terminals |
摘要 |
A memory circuit (<bold>14</highlight>) having features specifically adapted to permit the memory circuit (<bold>14</highlight>) to serve as a video frame memory is disclosed. The memory circuit (<bold>14</highlight>) contains a dynamic random access memory array (<bold>24</highlight>) with buffers (<bold>18, 20</highlight>) on input and output data ports (<bold>22</highlight>) thereof to permit asynchronous read, write and refresh accesses to the memory array (<bold>24</highlight>). The memory circuit (<bold>14</highlight>) is accessed both serially and randomly. An address generator (<bold>28</highlight>) contains an address buffer register (<bold>36</highlight>) which stores a random access address and an address sequencer (<bold>40</highlight>) which provides a stream of addresses to the memory array (<bold>24</highlight>). An initial address for the stream of addresses is the random access address stored in the address buffer register (<bold>36</highlight>).
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申请公布号 |
US2003196067(A1) |
申请公布日期 |
2003.10.16 |
申请号 |
US20030452339 |
申请日期 |
2003.06.02 |
申请人 |
HASHIMOTO MASASHI;FRANTZ GENE A.;MORAVEC JOHN VICTOR;DOLAIT JEAN-PIERRE |
发明人 |
HASHIMOTO MASASHI;FRANTZ GENE A.;MORAVEC JOHN VICTOR;DOLAIT JEAN-PIERRE |
分类号 |
G11C7/10;G11C8/02;H04B7/185;(IPC1-7):G06F12/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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