| 摘要 |
An analog filter comprising a first arithmetic operation section 2-1 consisting of a plurality of sets of processing circuit being cascade connected, each processing circuit having an S/H circuit of plural stages for holding a DELTA UNION -modulated signal and an analog adder for adding the input and output signals of the S/H circuit, in which the number of stages of the S/H circuits 11-1, 14-1, 17-1 and 20-1 decreases toward the end of cascade connection, and a second arithmetic operation section 2-2 configured in the same way, which are cascade connected. By using such an analog filter, over-sampling and convolution of a DELTA UNION -modulated signal are conducted so that the envelope of the filter output may be a quadratic curve of finite carrier that converges to zero at finite sampling points to prevent phase distortion of an LPF and a discretization error due to a conventional function. Compared with a conventional circuit for over-sampling and convolution, the number of stages of the S/H circuits and the number of adders are small. <IMAGE>
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