发明名称 CMI CODE DECODING CIRCUIT
摘要 PURPOSE:To decode correctly even a CMI code including 0 violation bit by counting a bit number subjected to violation and comparing it with a preset violation number and inverting the phase of a clock being the decoding of the CMI code. CONSTITUTION:A 1 violation detection means 101 detects the violation of code 1 at a CMI code input. A 0 violation detection means 103 uses a clock selected by a clock selection means 102 to detect the code 0 violation. The output of 0 violation of the means 101 and the output of the 0 violation detection means 103 count the number of violations in one frame by a violation detecting means 104. A deciding means 105 compares the violation number counted by the violation count means 104 with the preset violation number and when they are dissident, the selection of the clock by the means 102 is inverted.
申请公布号 JPS6268336(A) 申请公布日期 1987.03.28
申请号 JP19850207843 申请日期 1985.09.20
申请人 FUJITSU LTD 发明人 ITO KAZUHIKO;KATSUYAMA TSUNEO;HAYAMI SHICHIRO
分类号 H04L25/49;H03M5/04;H03M5/12;H04L7/00;H04L7/02;H04L7/08 主分类号 H04L25/49
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