| 摘要 |
PURPOSE:To simplify constitution, to improve reliability and to reduce cost by using 2-stage of frequency dividers each comprising a binary counter so as to frequency-divide a clock pulse having a frequency being 4 times the carrier frequency. CONSTITUTION:A frequency divider 1 of 2-stage constitution consisting mainly of binary counters, D type FFs 101, 102, and an output Q of each FF is fed back individually to the data input via OR gates 103, 104 and NAND gates 105, 106. Further, a clock pulse having a frequency being 4 times the carrier frequency is frequency-divided via the frequency divider 1 to generate the carrier and the addition output of modulo 4 between a 2-bit consecutive data and outputs from each stage of the frequency divider 1 is obtained. Then each stage of the frequency divider 1 is controlled by a corresponding order depending on each bit order of the added output to set the state of each stage. Thus, the constitution is simplified, the cost is reduced and the reliability is improved.
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