| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a data receiving circuit in which a low speed transmission signal can be prevented from being interrupted upon occurrence of a trouble in the master clock. <P>SOLUTION: A phase monitoring section 6 monitors the write timing and read timing of a buffer memory 4 in a destuff section 2 and delivers a count to an apparatus control section 9 where a decision is made whether a slip trouble is occurring or not. When a slip trouble is occurring, the apparatus control section 9 controls a clock switching section 8 to make a switch immediately from a retiming clock to a DPLL clock thus preventing a low speed transmission signal from being interrupted. <P>COPYRIGHT: (C)2004,JPO |
