| 摘要 |
The component (C) comprises several complementary MOS transistors implemented or complementary substrates whereon the substrate potentials (VPWELL, VNWELL) are applied. The component (C) is put in waiting mode by decreasing the higher potential and increasing the lowre potential while the substrate potentials remain unchanged. The integrated circuit comprises the component (C), where the first potential of substrate (VDD0 or VSS0) is applied on a substrate of the first type component, and a potential limiter (R1) provides the component (C) as a substrate (VDD0 or VSS0), or the first limited potential (VDD1 or VSS1). The second potential of substrate (VSS0 or GND0) is applied to a substrate of the second type (p or n), and a potential limiter (R2) provides the supply potential (VSS or VDD), which is equal to the second potential of substrate (VSS0 or VDD0), or the second limited potential (VSS1 or VDD1). The potential limiter (R1) comprises a transistor (P0) whose source and substrate receive the first potential of substrate (VDD0), the gate receives a control signal (/REGUL) representative of the mode of functioning, and the first supply potential (VDD) is produced on the drain of the transistor; a transistor (N3) whose drain is connected to the source of the transistor (P0), and the source is connected to the gate by the intermediary of an inverter (11). The potential limiter (R2) comprises a transistor (N0) whose source and substrate receive the second potential of substrate (VSS0), the gate receives a control signal (REGUL), and the second supply potential (VSS) is produced on the drain of the transistor; and a transistor (P3) whose drain is connected to the source of the transistor (N0), and the source is connected to the gate by the intermediary of an inverter (I2). |
