| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an ideal clock extraction circuit which commits no errors, even when a period having no data transition is long, operates stably in equilibrium, and has high follow-up property when large correction is needed. <P>SOLUTION: The circuit is provided with a phase comparator 110 for detecting the phase difference between reception data and an extraction clock, frequency reduction device 120 for reducing the frequency of the comparator 110, control signal generator 130 for monitoring the frequencies of frequency reduction output, and generating a signal for adjusting the phase of the extraction clock to be small, when a signal for advancing the phase and a signal for delaying the phase are uniformly outputted and adjusting the phase of the extraction clock to be large, when many more either type of the signals are outputted than the other signal, phase control signal 140 for outputting the extraction clock having adjusted phase upon reception of the control signal, and frequency divider 150 for dividing the extraction clock output. The proportion of frequency reduction of the device 120 is equal to a frequency division ratio of the divider 150. <P>COPYRIGHT: (C)2004,JPO |
