| 摘要 |
A frequency divider circuit (11) has an input port for an input signal (FO) to be divided, an output port for a divided signal (FDIV), and means (12-19) fo r providing a variable division ratio control signal (N+C) and a residual quantization error signal (R), applying the variable division ratio control signal (N+C) to a control port of the frequency divider, and using the residual quantization error signal (R) to cancel phase error in the divided signal. Both the variable division ratio control signal (N+C) and the residu al quantization error signal (R) are dithered.
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