发明名称 |
BUILT-IN-SELF-TEST CIRCUITRY FOR TESTING A PHASE LOCKED LOOP CIRCUIT |
摘要 |
A built-in-self-test circuit (11) aids in testing a phase locked loop circuit (10). The phased locked loop has a plurality of frequency multipliers. The built-in-self-test circuit (11) includes a frequency divider (24) and a multiplexer (25). The frequency divider (24) has a plurality of divide-by-counters. For each frequency multiplier within the plurality of frequency multipliers there is a corresponding divide-by-counter. A ratio of a multiplier for each frequency multiplier to a divider (24) of its corresponding divide-by-counter is a constant for all frequency multipliers and corresponding divide-by-counters. When a frequency multiplier within the plurality of frequency multipliers is selected, the multiplexer (25) selects its corresponding divide-by-counter to produce a test output clock (14). |
申请公布号 |
WO0233433(A3) |
申请公布日期 |
2003.10.09 |
申请号 |
WO2001EP11617 |
申请日期 |
2001.10.09 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
OTT, RUSSELL |
分类号 |
G01R31/28;G01R31/3183;G01R31/3187;H03L7/08;H03L7/095;H03L7/16 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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