A SYSTEM AND METHOD TO ENHANCE MANUFACTURING TEST FAILURE ANALYSIS WITH DEDICATED PINS

摘要

The present invention is a scan test chain intermediate debugging system and method that facilitates simplified debugging of internal component scan test results with minimal impacts to normal operations and manufacturing processes. The scan test chain intermediate debugging system and method of the present invention enhances internal scan test analysis on internal scan test chains included in digital circuits and is compatible with scan test methodologies. One embodiment of the present invention includes a scan test chain intermediate debugging system including a test vector debugging control circuit (e.g., a multiplexer), a supplemental scan test output port and an intermediate control signal port. The test vector debugging control circuit selectively provides a communication path from an indicated intermediate scan test chain signal to the supplemental scan test output port. The intermediate scan test signal is a measurement or logical value captured from an intermediate point in the scan test chain. The intermediate control signal port provides a communication path for a control signal that directs the test vector debugging control circuit which intermediate scan test signal to transmit to the supplemental scan test output port. The supplemental scan test output port operates to transmit intermediate scan test signals off of the IC. By selectively transmitting one of the intermediate scan test chain signals off of the IC, the scan test chain intermediate debugging system and method facilitates greater granularity of test vector results and assists scan test analysis including debugging indications of faults.