发明名称 Built-in self test circuit
摘要 A built-in self test circuit (BIST circuit) in an LSI includes a verification test pattern generator for generating verification test pattern which is used for verifying the connections in the LSI including the BIST circuit in the design stage thereof, and another test pattern generator which is used to test the function of the LSI.
申请公布号 US2003191998(A1) 申请公布日期 2003.10.09
申请号 US20030402956 申请日期 2003.04.01
申请人 NAKAMURA YOSHIYUKI 发明人 NAKAMURA YOSHIYUKI
分类号 G01R31/28;G01R31/3181;G01R31/3183;G01R31/3185;G01R31/3187;G11C29/10;G11C29/12;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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