| 摘要 |
A multilevel metal interconnect structure and method of fabrication for semiconductor integrated circuits. A first horizontal metal interconnector line, for example copper, is topped by a stack of horizontal insulating layers alternating between etch stop and dielectric layers so that the bottom etch stop layer is selected to be etchable at a first rate by a selected etchant, while the upper etch stop layers are selected to be etchable at a second rate by the same selected etchant. Preferably, the first etch rate is about ten times faster than the second etch rate. When a vertical trench and via are etched into the stack, the bottom stop layer can be opened for contact to the first metal line without etching the other stop layers substantially. Trench and via are finally filled with metal, for instance copper, to form the second level interconnector line and the via contact to the first level metal line.
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