| 摘要 |
It is intended to provide a control method of a semiconductor memory device and a semiconductor memory device capable of shortening pre-charge operation time that comes after termination of successive data access operation, namely, successive data read/write operation, without causing deterioration of restore voltage to memory cells and delay of initial data access time. An activated word line WL0 is deactivated with appropriate timing that is between time after bit line pairs (BL0 and /BL0, . . . BLN and /BLN) are differentially amplified up to full amplitude voltage level and time where column selecting lines CL0, . . . CLN are selected. That is, deactivation time tauA for the word line can be embedded in a period of successive data access operation. Pre-charge operation can be terminated within time that is a sum of deactivation time tauAB of a sense amplifier and equalizing time tauC of the bit line pairs. Thereby, pre-charge period can be shortened.
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