A NOVEL HIGHLY-INTEGRATED FLASH MEMORY AND MASK ROM ARRAY ARCHITECTURE

摘要

A memory cell device (Fig.4) is achieved. The memory cell device (M41) comprises a first transistor (M41a) having gate, drain, and source. A second transistor (M41b) has gate, drain, and source. The first transistor drain is coupled to an array bit line (41). The second transistor source is coupled to an array source line (43). The first transistor source is coupled to the second transistor drain. The first transistor (M41a) and the second transistor (M41b) comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.