| 摘要 |
<p>The invention provides for a clock monitoring circuit comprising a first flip-flop circuit for latching and outputting an input signal when a given transition of a clock signal occurs between its two logic levels, a second flip-flop circuit for latching and outputting the output signal of the first flip-flop circuit when a given transition of the clock signal occurs between its two logic levels, delay means for delaying the output signal of the second flip-flop circuit by a time interval that is shorter than a predetermined period of the clock signal and for outputting the resultant signal as an input signal to the first flip-flop circuit, and a gate circuit for receiving the output signal of the first flip-flop circuit and the output signal of the second flip-flop circuit, and for outputting a signal of a first logic level when the period of the clock signal is equal to, or greater than, the predetermined time interval and for outputting a signal of a second logic level when the period of the clock signal is shorter than the predetermined time interval. <IMAGE></p> |
