发明名称 BARREL SHIFTER HAVING PARITY-BIT GENERATOR
摘要 PURPOSE: To eliminate the delay between the timing of calculation of parity and timing wherein data become unusable in a computer. CONSTITUTION: This barrel shifter is obtained by dividing input words A and B. Each barrel shifter is equipped with a parity word generating circuit (116) which consists of parity bits combined with one of plural sets of (n) bits and a parity matrix (115) combined with a shift matrix (113) which generates successive (n)-bit groups of parity bits outputted through a parity word output line Q and constituting an output word S.
申请公布号 JPH04218829(A) 申请公布日期 1992.08.10
申请号 JP19900407407 申请日期 1990.12.07
申请人 BULL SA 发明人 AREN GURENE
分类号 G06F7/00;G06F5/00;G06F7/76;G06F11/10 主分类号 G06F7/00
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