| 摘要 |
The invention relates to an apparatus and a method for bit mapping of an output data signal with respect to an ordering of a serial higher bitrate input data signal with an incoming clock signal, whereby the ordering of output data signal is initiated by a frequency division operation of the incoming clock signal and the phase relationship between the input data signal and the incoming clock signal. Thereby the division operation of the incoming clock signal comprises an inversion of the divided clock signal to perform a barrel shifting operation. <??>The inventive apparatus for transferring a multiplexed signal to a multiplicity of lower bitrate output signals comprises a receiving unit, wherein a high frequency signal is received and at least one demultiplexing unit adapted to demultiplex the received signal into a multiplicity of lower bitrate output signals according to a certain demultiplexing ratio as given by 1:2<k> with a power k being an element of the quantity of natural numbers. Also at least one frequency dividing unit and an output unit with at least one output channel for emitting the multiplicity of lower bitrate output signals. The at least one exchanging unit is adapted to reorder the multiplicity of output signals to the at least one output channel corresponding to the ordering as given by the incoming high frequency signal, whereby the exchanging unit is driven by a bitmapping monitor located at the output side of the apparatus.
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