Multiple synthesized clocks with fractional ppm control from a single clock source

摘要

A system (200) for generating multiple synthesized clocks having an input terminal (230) for receiving a reference signal, a phase locked loop circuit (108) coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals (250) that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator (205) coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases. <IMAGE>