发明名称 |
Low power precharge scheme for memory bit lines |
摘要 |
A low power memory bit line precharge scheme. A memory bit line is coupled to a first read precharge device. A second write precharge device is also coupled to the memory bit line and is to be enabled only in response to a memory write operation. The first read and second write precharge devices are sized such that their combined drive strength is sufficient to precharge the first memory bit line during a precharge period following a write operation.
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申请公布号 |
US6631093(B2) |
申请公布日期 |
2003.10.07 |
申请号 |
US20010895361 |
申请日期 |
2001.06.29 |
申请人 |
INTEL CORPORATION |
发明人 |
KUMAR SUDARSHAN;LAN JIANN-CHERNG;JIANG WENJIE;MEHTA GAURAV;MADHYASTHA SADHANA |
分类号 |
G11C7/12;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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