发明名称 |
Cache architecture for pipelined operation with on-die processor |
摘要 |
Architecture for a cache fabricated on a die with a processor including a plurality of cache banks, each containing a plurality of storage cell subarrays, the cache banks being arranged in physical relationship to a central location on the die that provides a point for information transfer between the processor and the cache. A data path provides synchronous transmission of data to/from the cache banks such that data requested by the processor in a given clock cycle is received at the central location a predetermined number of clock cycles later regardless of which cache bank in the cache the data is stored.
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申请公布号 |
US6631444(B2) |
申请公布日期 |
2003.10.07 |
申请号 |
US20010894513 |
申请日期 |
2001.06.27 |
申请人 |
INTEL CORPORATION |
发明人 |
SMITS KENNETH R.;BHUSHAN BHARAT;NEMANI MAHADEVAMURTY |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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