发明名称 Twin MONOS array metal bit organization and single cell operation
摘要 In the present invention a twin MONOS metal bit line array is read and programmed using a three dimensional programming method with X, Y and Z dimensions. The word line address is the X address. The control gate line address is a function of the X and Z addresses, and the bit line address is a function of the Y and Z addresses. Because the bit lines and the control gate lines of the memory array are orthogonal a single cell can be erased with an adjacent memory, having the same selected bit and control gate lines, being inhibited from erase by application of the proper voltages to unselected word, control gate and bit lines.
申请公布号 US6631088(B2) 申请公布日期 2003.10.07
申请号 US20020190634 申请日期 2002.07.08
申请人 HALO LSI, INC. 发明人 OGURA SEIKI;SAITO TOMOYA;OGURA TOMOKO
分类号 G11C16/06;G11C16/02;G11C16/04;G11C16/08;G11C16/14;G11C16/24;H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):G11C16/04 主分类号 G11C16/06
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