| 摘要 |
A method of testing field programmable gate array (FPGA) resources and identifying faulty FPGA resources during normal on-line operation includes configuring an FPGA into a working area and an initial self-testing area. The working area maintains normal operation of the FPGA throughout testing and identifying of the resources. Within the initial and subsequent self-testing areas, the FPGA resources are initially tested for faults. Upon detection of a fault in the FPGA resources, the initial self-testing area resources are reconfigured or subdivided and further tested in order to identify the faulty resource. Dependent upon the further test results, the FPGA resources may be further subdivided and tested until the faulty resource is identified. Once the faulty resource is identified, the FPGA is reconfigured to replace unusable faulty resources or to avoid faulty modes of operation of partially faulty resources diagnosed during further testing. In this manner, partially faulty resources are allowed to continue operation in a diminished capacity to enhance fault tolerance. After testing each of the FPGA resources located within the initial self-testing area for faults, identifying the faulty resources, and in some instances diagnosing faulty modes of operation of the faulty resource, the FPGA is reconfigured such that a portion of the working area becomes a subsequent self-testing area and the initial self-testing area replaces that portion of the working area. In other words, the self-testing area roves around the FPGA testing its resources in a continuous manner.
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