| 摘要 |
PURPOSE: A redundancy circuit is provided to share a corrective address wire and reduce a total size of a chip by loading the corrective address information corresponding to each redundancy column decoder. CONSTITUTION: A redundancy circuit includes the first fuse enable signal generation portion(401), the first AND gate(402), the first fuse circuit portion(403), the first latch portion(404), the first comparison portion(405), the second AND gate(406), the second fuse enable signal generation portion(407), the third AND gate(408), the second fuse circuit portion(409), the second latch portion(410), the second comparison portion(411), and the fourth AND gate(412). The first fuse enable signal generation portion(401) generates an enable signal. The first AND gate(402) is used for performing an AND operation for the first signal and the enable signal. The first fuse circuit portion(403) includes a plurality of fuse circuits to generate a corrected address signal. The first latch portion(404) includes a plurality of latches to maintain the corrected address signal. The first comparison portion(405) includes a plurality of XNOR gates to perform an XNOR operation. The second AND gate(406) is used for performing the AND operation for output signals of the first comparison portion(405). The second fuse enable signal generation portion(407) generates the enable signal. The third AND gate(408) is used for performing the AND operation for the second signal and the enable signal of the second fuse enable signal generation portion(407). The second fuse circuit portion(409) includes a plurality of fuse circuits to generate the corrected address signal. The second latch portion(410) includes a plurality of latches to maintain the corrected address signal. The second comparison portion(411) includes a plurality of XNOR gates to perform the XNOR operation. The fourth AND gate(412) is used for performing the AND operation for output signals of the second comparison portion(411).
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