MEMORY TARGET DEVICE AND DATA TRANSFER SYSTEM

摘要

PROBLEM TO BE SOLVED: To simplify a data transferring part inside a memory target device, especially the circuit of a buffer control part even in the case of using a 64-bit PCI (peripheral components interconnect) bus. SOLUTION: The CPU-A 31 of the memory target device 2 side and the CPU-B 34 of a data transferring device 3 or 4 side performs communication about bit width, and when it is determined whether PCI bus transfer is 64 bits or 32 bits, the CPU-A 31 sets a switch bit pci64en of PCI64bit Enable existing in the memory target device 2 in either 64 bits or 32 bits. The switch bit pci64en is inputted to a Target Read DMA control part 7 to determine an operation mode. It is thereby possible to easily control whether an operation to a 64-bit data buffer included in the Target Read DMA control part 7 is for 64 bits or for 32 bits. COPYRIGHT: (C)2004,JPO