| 摘要 |
PROBLEM TO BE SOLVED: To reduce the leak current in MOS transistors used for a logic evaluator in a logic circuit and suppress the rise of a noise voltage to expand the operation margin. SOLUTION: A synchronous logic circuit comprises: a pMOS transistor M1 connected between a power source terminal Vdd and a first node N1 with a clock signal CLK inputted to its gate; an nMOS transistor M2 connected between a ground terminal Vss and a second node N2 with the clock signal CLK inputted to its gate; and a logic evaluator 10 composed of nMOS transistors M31, 32 connected in parallel between the nodes N1, N2 with input signals IN1, IN2 fed to the gates of both transistors. A pMOS transistor M4 is inserted between the bodies of the nMOS transistors M31, 32 with the Vss connected to its gate. COPYRIGHT: (C)2004,JPO
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