| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase comparator and a PLL circuit which surely enable phase comparison of a high speed reference signal with a comparison signal by using a circuit of a low operation speed. <P>SOLUTION: The phase comparator is provided with two edge trigger type RS flip-flops 11, 12 and a logic operation circuit 13. A data signal as the reference signal and a clock signal which has a 1/n times frequency of the data signal and is used as the comparison signal are input in the flip-flop 11. The data signal as the reference signal and a signal which is obtained by inverting the clock signal and used as the comparison signal are input in the flip-flop 12. The logic operation circuit 13 calculates a logical product or a logical sum of output signals of the flip-flops 11, 12, thereby generating an error signal having a unique pulse width corresponding to a phase difference every rise edge of the data signal. <P>COPYRIGHT: (C)2004,JPO |
