| 摘要 |
<P>PROBLEM TO BE SOLVED: To enhance the transmission rate of a system by securely receiving an input signal in synchronism with a clock signal. <P>SOLUTION: A variable delay circuit delays a first input signal according to a delay adjustment signal and outputs the delayed signal as a first delayed signal. A judgment circuit outputs an incremental signal or a decremental signal according to the phase difference between the first delayed signal and the clock signal. A delay adjustment circuit generates the delay adjustment signal that adjusts the variable delay circuit according to the incremental signal or the decremental signal. Consequently, even when the timing of the first input signal and the clock signal is deviated due to the changes of the temperature and voltage, etc., a first receiving circuit securely receive the first input signal by synchronizing it with the clock signal. Since an establishment period of the first input signal to the clock signal is minimized, the frequency of the clock signal is prevented from being restricted by establishment time. Consequently, the transmission rate of the first input signal is enhanced. <P>COPYRIGHT: (C)2004,JPO |
